1. Field of the Invention
The present invention relates to a semiconductor memory device exemplified for example by DRAM (Dynamic Random Access Memory), and in particular to a semiconductor memory device that stores multi-value data having more than two values in a memory cell.
2. Description of the Related Art
A 4-value DRAM disclosed in Japanese Unexamined Patent Application, First Publication, No. Hei 9-320280, is a first example of conventional art related to multi-value semiconductor memory devices. FIG. 21 extracts from the structure of the DRAM as a whole one memory cell and a circuit for reading and writing that memory cell, to illustrate the circuit that appears in this publication more schematically. Thus, a summary of the read operation from the memory cell will be described below.
Moreover, the memory cell 100 shown in the figure holds a potential depending on the data it stores, and for example, when the electric source potential is VCC, holds 0, (1/3) VCC, (2/3) VCC, and VCC according respectively to the data 00, 01, 10, and 11. In addition, in this first example of conventional art, a layered bit line structure comprising a main bit line and a sub-bit line is used, and a sense amplifier structure comprising a main sense amplifier (not illustrated) and a sub-sense amplifier 101 is used.
First, the main bit lines GBLT and GBLN and the sub-bit lines BLTU, BLTL, BLNU, and BLNL are all precharged to (1/2) VCC. Next, by setting the signal TGL at L level, transistors (sometimes abbreviated "Tr" hereinbelow) Q100 and TrQ101 are turned OFF. Thereby, the sub-bit lines BLTU and BLTL, which are on either side of the sense amplifier 101, are cut off from each other, and the sub-bit lines BLNU and BLNL are cut off from each another. Next, the potential held in the memory cell 100 is read out to the sub-bit line BLTU by activating the word line WL, and a difference in potential is generated between the sub-bit lines BLNU and BLTU that depends on the data stored by the memory cell 100.
Next, the signal RS corresponding to the lead switch is set at H level, and the TrQ 102 and TrQ 103 in the sub-sense amplifier 101 are turned ON. Thereby, the sub-sense amplifier 101 transmits to the main bit lines GBLT and GBLN the sense results depending on the difference in potential between the sub-bit lines BLNU and BLTU via TrQ 104 and TrQ 105, and the above-described TrQ 103 and TrQ 102. Thus, the signal RS is restored to L level, and at the same time, reading of the upper bit is carried out by amplifying the difference in potential between the main bit lines GBLT and GBLN by the main sense amplifier (not illustrated). At this time, simultaneously the signal CPS is set at H level and TrQ 106 and TrQ 107 are turned ON, and via capacitors 102 and 103 that hold a capacitance ("1/3 Cs" in the figure) of 1/3 of the memory cell 100, the potential fluctuation of the main bit lines GBLT and GBLN is respectively transmitted to the sub-bit lines BLNU and BLTU. Thereby, if the data stored in memory cell 100 is 10 or 01, the size relationship of the potential between the sub-bit lines BLNU and BLTU reverses. Subsequently, by restoring the signal CPS to L level, the main bit lines GBLT and GBLN are cut off from each other and the sub-bit lines BLNU and BLTU are cut off from each other, and at the same time by setting the signal TGU at L level and tuning TrQ 108 and TrQ 109 OFF, the sub-bit lines BLTU and BLNU are cut offfrom the sub-sense amplifier 101. Next, TrQ 110 and TrQ 111 are turned ON by setting the signal WSU at H level, and the amplified potential of the main bit lines GBLT and GBLN are respectively written to the sub-bit lines BLTU and BLNU. Next, after restoring the signal WSU to L level, by setting the signal RS at H level, the results of the sensing that depends on the difference in potential between the sub-bit lines BLNL and BLTL are transmitted to the main bit lines GBLT and GBLN. In this manner, like the case of the upper bit, reading of the lower bit is carried out.
Next, TrQ 112 and TrQ 113 are turned on by setting the signal WSL at H level, and the potential of the main bit lines GBLT and GBLN are written to the sub-bit lines BLTL and BLNL. At this time, simultaneously TrQ 110 and TrQ 101 are turned ON by setting the signal TGL at H level. Next, by setting the signal TGU at H level, the sub-bit lines BLTU and BLTL are connected and the sub-bit lines BLNU and BLNL are connected. Next, by setting the signal TGU to H level, the sub-bit lines BLTU and BLTL are connected and the sub-bit lines BLNU and BLNL are connected. As a result, capacitive coupling of both bit lines occurs, and the potential of the sub-bit line BLTU and the potential that is held in the memory cell 100 before reading are equalized. Thus, by activating the word line WL, the potential of memory cell 100 which has been destroyed by this reading operation is rewritten from the sub-bit line BLTU.
As a second example of conventional art related to a multi-value semiconductor device, the technology disclosed, for example, in Masakazu Aoki et al., "A 16-Levels/Cell Dynamic Memory." IEEE International Solid-State Circuits Conference (ISSCC), 1985, Digest of Technical Papers, pp. 246-247, is known. This publication discloses a method wherein the reading of multi-value data stored in a memory cell and writing multi-value data into a memory cell is carried out by a stepwise change by oscillating the potential of the word line to cause a stepwise change that depends on the data stored in the memory cell.
As described above, in the first example of conventional art, the result of sensing the upper bit is fed back in order to sense the lower bit. Due to this, in the first example of conventional art, a feedback capacitor must be provided for each sub-sense amplifier. Here, as described above, the feedback capacitor has a capacitance of "1/3 Cs", corresponding to 1/3 the capacitance Cs of the memory cell, and thus a memory cell that differs from the standard memory cell is required. In the first example of conventional art, a capacitor having this special capacitance is effectively realized by serially connecting three capacitors equivalent to those provided in the memory cell. However, when the capacitor is realized by such a serial connection, a large area is required, and this in turn causes an increase in cost.
On this point, one could consider making the capacitor having this capacitance using the gate capacitance of transistors. However, because the properties of the variance in gate capacitance and the properties of the variance in memory cell capacitance differ from each other, in a method that realizes this capacitor using gate capacitance, the variance of capacitance exceeds the permissible range, and there are problems in really applying this to actual products. In addition to the problem of this variance in capacitance, there is the problem that the variance in the capacitance of this feedback capacitor influences the yield. Furthermore, in comparison to the main sense amplifier, because feedback capacitors must be respectively provided for a plurality of sub-sense amplifiers, the above-described problem becomes severe.
In the above-described second example of conventional art, there is the problem that the yield is low because the variance of the threshold of the memory cells, which are much more numerous than SSAs, influences the operational margin.